DACs are typically constructed of an array of current source transistors that produce output currents of weighted values that represent bits in a binary word. High resolution DACs typically employ weighted current sources in which the ratio of the most significant current bit I.sub.MSB, to the least significant current bit, I.sub.LSB, ranges from 128:1, in the case of an eight-bit DAC, to as high as 32,768:1, in the case of a sixteen-bit DAC. In general terms, I.sub.MSB /I.sub.LSB =2.sup.(N-1), where N is the number of bits.
FIG. 1 shows a binary-weighted current source array circuit 10, which is based on simple gate-width scaling of depletion mode field effect transistors ("FETs"). Circuit 10 includes constant-current source FETs Q.sub.0, Q.sub.1, Q.sub.2, . . . , Q.sub.N-2, Q.sub.N-1, where N is the number of bits. Transistors Q.sub.0, Q.sub.1 . . . , Q.sub.N-1 conduct currents I.sub.MSB, I.sub.MSB-1, I.sub.MSB-2 . . . , I.sub.LSB+1, I.sub.LSB, respectively, whose magnitudes correspond to the binary-weighted bits. The gates of transistors Q.sub.0, Q.sub.1, . . . , Q.sub.N-1 are each biased by the same reference voltage, V.sub.ref, which controls the absolute magnitudes of currents I.sub.MSB, I.sub.MSB-1, . . . , I.sub.LSB. Although transistors Q.sub.0, Q.sub.1, . . . , Q.sub.N-1 are FETs, the principles discussed herein also apply to DACs using bipolar junction transistors ("BJTs").
The gate widths of Q.sub.0, Q.sub.1, . . . , Q.sub.N-1 are equal to W.sub.MSB /2.sup.i, where i=bit number and the bit number represents the order or "degree of significance" of the bit. Therefore, for an eight-bit DAC, the gate width of Q.sub.0, which provides the current for the most significant bit, i.e., bit 7, is W.sub.MSB /2.sup.0 =W.sub.MSB. The gate width of Q.sub.1 is W.sub.MSB /2.sup.1 =W.sub.MSB /2. The gate width for the least significant bit is equal to W.sub.LSB =W.sub.MSB /2.sup.7. In a typical embodiment, the value of the drain-to-source voltage, V.sub.DS, and the gate width of each transistor are chosen so that the value of the gate-to-source voltage, V.sub.GS, of each transistor is zero for the desired current.
The value of each current is equal to I.sub.MSB /2.sup.i, where i=bit number which is as defined above. The value of current for the most significant bit, e.g., bit 0 in an eight-bit DAC, is I.sub.MSB /2.sup.0 =I.sub.MSB. The value of current for bit 1 is I.sub.MSB-1 =I.sub.MSB /2.sup.1 =I.sub.MSB /2. The value of current for the least significant bit, i.e., bit 7, is I.sub.LSB =I.sub.MSB /2.sup.7.
Source degeneration resistors having values R.sub.s, 2R.sub.s, 4R.sub.s, . . . , 2.sup.N-1 R.sub.s are connected between transistors Q.sub.0, Q.sub.1, . . . , Q.sub.N-1, respectively, and V.sub.SS, which is a more negative voltage than the reference input voltage, V,.sub.ref, to enhance scaling (ratioing) among the various current sources.
The number of bits that may be employed in a DAC using only width scaling as the means of establishing the bit currents is severely limited because of the constraints of minimum and maximum acceptable dimensions for semiconductor devices. A gallium arsenide ("GaAs") transistor, for example, does not produce linear scaling of output current as a function of gate width if the gate width is "too narrow," e.g., a typical value being less than 10 microns. Therefore, unless the width w.sub.MSB is unacceptably large, the DAC of circuit 10 cannot have very many bits if w/2.sup.i is no smaller than 10 microns. For example, if the least significant bit (i.e., bit 7) of a simple width-scaled eight-bit DAC has a gate width w.sub.LSB of 10 microns, then the gate width of bit 6 is 2 w.sub.LSB =20 microns, the gate width of bit 5 is 4 w.sub.LSB =40 microns, the gate width of bit 4 is 8 w.sub.LSB =80 microns, the gate width of bit 3 is 16 w.sub.LSB =160 microns, the gate width of bit 2 is 32 w.sub.LSB =320 microns, the gate width of bit 1 is 64 w.sub. LSB =640 microns, and the gate width of the most significant bit, bit 0, w.sub.MSB =1,280 microns. Depending on the application, gate widths in excess of 100 to 300 microns are considered to be an unacceptably inefficient use of the chip material, and/or the associated currents are unacceptably large. In this case, only one-half of the bits of the eight-bit DAC would have acceptable gate widths of less than 100 microns, i.e., a 4 or 5 bit DAC would present the largest "acceptable" device.
On the other hand, if the most significant bit (i.e., bit 0) of a simple width scaled eight-bit DAC has a gate width w.sub.MSB of 100 microns, then the gate width of bit 1 is w.sub.MSB /2=50 microns, the gate width of bit 2 is w.sub.MSB /4=25 microns, the gate width of bit 3 is w.sub.MSB /8=12.5 microns, the gate width of bit 4 is w.sub.MSB /16=6.25 microns, and the gate widths of bits 5, 6, and 7 are all less than 10 microns. Therefore, only bits 4-7 of the eight-bit DAC would have acceptable gate widths of 10 microns or greater.
Referring to FIG. 2, an approach to overcoming the constraints associated with simple width scaling involves the use of a weighted cascode current divider 20 which, in this example, conducts currents I.sub.a (largest), I.sub.b, I.sub.c, I.sub.d, and I.sub.e (smallest). Currents I.sub.a -I.sub.e are summed at node 26 to become current I.sub.s, which is conducted by a master current source transistor 28. Currents I.sub.a -I.sub.e are conducted through transistors 30a, 30b, 30c, 30d, and 30e, respectively, and source degeneration resistors R.sub.s /16, R.sub.s /8, R.sub.s /4, R.sub.s /2, and R.sub.s, respectively.
The gate widths of transistors 30a-30e are 16 w, 8 w, 4 w, 2 w, and w, respectively. The gate width of transistor 28 is w. The sum of currents I.sub.a -I.sub.e is equal to current I.sub.s, the upper limit of which is constrained by the width of transistor 28. The value of current I.sub.s is controlled by adjusting V.sub.ref. The relative magnitudes of currents I.sub.a -I.sub.e are set by the width or area ratios of the cascode transistors 30a-30e. Because the widths of the cascode transistors 30a-30e do not establish the absolute currents, reasonably sized transistors, e.g., w=10 to 15 microns and 16 w=160 to 240 microns, may be used for transistors 30a-30e, resulting in output currents corresponding to effective scaled widths of w/2, w/4, w/8, w/16 and w/32 which can be much smaller than the width of physically realizable devices.
The techniques of FIGS. 1 and 2 may be combined to obtain a wide range of current ratios, as shown in FIG. 3. Referring to FIG. 3, an eight-bit binary weighted current source array circuit 34 provides currents I.sub.0 (MSB), I.sub.1, I.sub.2, I.sub.3, I.sub.4, I.sub.5, I.sub.6, and I.sub.7 (LSB). Currents I.sub.0 -I.sub.3 are provided by a binary-weighted simple width-scaled current source array 36, which includes field effect transistors 44a, 44b, 44c, 44d, 48a, 48b, 48c, and 48d. Currents I.sub.4 -I.sub.7 are provided by a weighted cascode current divider 38 which is similar to circuit 20 in FIG. 2.
Currents I.sub.0 -I.sub.3 have the following relationship: I.sub.1 =I.sub.0 /2, I.sub.2 =I.sub.0 /4, and I.sub.3 =I.sub.0 /8. The values of currents I.sub.0 -I.sub.3 are determined by the gate widths and values of V.sub.DS of transistors 44a-44d and 48a-48d and by the values of reference voltage V.sub.ref and bias voltage V.sub.BIAS connected to the gates of transistors 44a-44d and transistors 48a-48d, respectively. The gate widths cf transistors 44a and 48a are 8 w, the gate widths of transistors 44b and 48b are 4 w, the gate widths of transistors 44c and 48c are 2 w, and the gate widths of transistors 44d and 48d are w. Width w may be chosen to be as small as allowed by the fabrication process, consistent with the criteria that it still provide linear scaling of drain current with gate width.
The parameters for transistors 44a-44d and 48a-48d are chosen as follows. The gate width 8 w of transistor 44a is chosen so that the desired current I.sub.0 will be produced with V.sub.GS =0 and V.sub.DS =2 volts. For purposes of illustration, choose the voltage V.sub.SS =-12 volts. The voltage drop across resistor 50a, which has resistance R.sub.s /8, is chosen to be 3 volts. Because V.sub.GS =0 for transistor 44, V.sub.ref is -9 volts. Because V.sub.DS =2 volts, the drain of transistor 44a is greater than or equal to -7 volts. Transistor 48a has the same gate width 8 w as does transistor 44a. Therefore, for transistor 48a, if V.sub.DS =2 volts, then V.sub.GS =0 volts, requiring V.sub.BIAS =-7 volts for consistency. The voltage at the drain of transistor 48a is greater than or equal to -5 volts.
Currents I.sub.1, I.sub.2, and I.sub.3 are set to be equal to I.sub.0 /2, I.sub.0 /4, and I.sub.0 /8, by setting the following values for transistors 44b-44d, 48b-48d, and resistors 50b, 50c, and 50d, respectively. Transistors 44b and 48b have width=4 w, 44c, 48c have width=2 w, and 44d, 48d have width=w. Source degeneration resistors 50b-50d have resistances R.sub.s /4, R.sub.s /2, and R.sub.s, respectively. The voltages at the drains, gates, and sources of transistors 48b-48d are equal to the voltages at the drain, gate, and source, respectively, of transistor 48a. The voltages at the drains, gates, and sources of transistors 44b-44d are equal to the voltages at the drain, gate, and source, respectively, of transistor 44a. Given these parameters, currents I.sub.0 -I.sub.3 each are "above the knee" on the flat saturation part of the I.sub.D vs. V.sub.DS FET characteristic curve, for their respective gate widths.
Currents I.sub.4 -I.sub.7 and I.sub.7 ' are conducted by transistors 56a, 56b, 56c, 56d, and 56e, respectively, of cascode current divider 38. Currents I.sub.4 -I.sub.7 have the following relationship: I.sub.5 =I.sub.4 /2, I.sub.6 =I.sub.4 /4, and I.sub.7 =I.sub.7 ' =I.sub.4 /8. The gates of transistors 56a-56d are each connected to voltage V.sub.BIAS. The gate widths of transistors 56a-56e are 8 w, 4 w, 2 w, w, and w, respectively. Source degeneration resistors 62a, 62b, 62c, 62d, and 62e, having resistances R.sub.sc /8, R.sub.sc /4, R.sub.sc /2, R.sub.sc and R.sub.sc, respectively, are connected between the sources of transistors 56a-56e, respectively, and node 66. Currents I.sub.4 -I.sub.7, and I.sub.7 ' are summed at node 66 to become current I.sub.3 '. Therefore, I.sub.4 +I.sub.5 +I.sub.6 +I.sub.7 +I.sub.7 '=I.sub.3 '. Ideally, current I.sub.3 ' is equal to I.sub.3, although in practice it will deviate from the value of I.sub.3. If current I.sub.3 40 is not equal to I.sub.3, then currents I.sub.4 -I.sub.7 will not have the correct proportional relationship with currents I.sub.0 -I.sub.3.
The reason why I.sub.3 ' might not equal I.sub.3 is as follows. The voltage at the drains of transistors 56a-56e is chosen to be greater than or equal to -5 volts, consistent with the bias at the drains of transistors 48a-48d. The magnitudes of currents I.sub.4 -I.sub.7, and I.sub.7 ' are each less than I.sub.DSS for their respective transistors 56a-56e, but are above the knee of the I.sub.d vs. V.sub.DS curve for transistors 56a-56e. Therefore, the voltages V.sub.GS, for transistors 56a-56e are less than zero, for example, -1 volt. Recall that the voltage V.sub.BIAS is equal to -7 volts. Therefore, the voltages at the sources of transistors 56a-56e will be equal to -6 volts. In order for there to be proper scaling between current I.sub.3 and currents I.sub.4, I.sub.5, I.sub.6, and I.sub.7, as described previously, it is desirable that there be close matching of the magnitudes of currents I.sub.3 and I.sub.3 '. For this close matching, both the physical dimensions of transistors 44d and 70, as well as their respective bias conditions V.sub.GS of transistor 44d compared to V.sub.GS of transistor 70 and V.sub.DS of transistor 44d compared to V.sub.DS of transistor 70 should be as closely matched as possible. In the case of the circuit topology shown in FIG. 3, the fact that transistors 56a-56e operate significantly below I.sub.DSS (i.e., V.sub.GS of transistors 56a-56e&lt;&lt;0 volts), while transistors 48a-48d operate at I.sub.DSS (i.e., V.sub.GS of transistor 44a-48d=0 volts), will virtually guarantee that V.sub.DS of transistor 44d.noteq.V.sub.DS of transistor 70, leading to I.sub. 3 .noteq.I.sub.3 ', and, hence, significant and unacceptable scaling error between current I.sub.3 and currents I.sub.4, I.sub.5, I.sub.6 and I.sub.7.
A partial solution to the problem of V.sub.DS of transistor 44d.noteq.V.sub.DS of transistor 70 involves the appropriate choice of the value of resistors 62a-62e such that I.sub.4 .multidot.R.sub.sc /8=I.sub.5 19 R.sub.sc /4=I.sub.6 .multidot.R.sub.sc /2=I.sub.7 .multidot.R.sub.sc =.vertline.V.sub.S56a -V.sub.S48d .vertline., where V.sub.S56a is the voltage of the source of transistor 56a and V.sub.S48d is the voltage of the source of transistor 48d. However, such a choice may only be correct for one particular temperature, power supply condition, and absolute value of I.sub.3 and I.sub.3 '. Variations in these parameters may result in a scaling error between I.sub.3 and I.sub.3 '. Furthermore, practical limitations on the size of resistors R.sub.sc, R.sub.sc /2, R.sub.sc /4, R.sub.sc /8 may force one to choose I.sub.4 .multidot.R.sub.sc /8=I.sub.5 .multidot.R.sub.sc /4=I.sub.6 .multidot.R.sub.sc /2=I.sub. 7 .multidot.R.sub.sc &lt;.vertline.V.sub.S56a -V.sub.S48d .vertline..multidot.In that case, one will be unable to reduce the offset between V.sub.DS of transistor 44d and V.sub.DS of transistor 70 to 0 volts.
Another partial solution to the problem of the voltage at the drains of transistors 44d and 70 not being equal, is to use one bias, V.sub.BIAS1, for transistors 48a-48d, and to use another bias, V.sub.BIAS2, for the gates of transistors 56a-56d. The difference between V.sub.BIAS1 -V.sub.BIAS2 is V.sub.OS. Voltage V.sub.OS is equal to the absolute value of V.sub.GS of transistors 56a-56e minus I.sub.5 R.sub.sc /8. The effectiveness of this technique depends upon the number of bits in the DAC. For example, the technique may work with a DAC having eight bits, but not more than eight bits. Further, the effectiveness of the technique is temperature, process, and power supply voltage dependent. Even in the best of conditions, the voltages at the drains of transistors 44d and 70 will be only approximately equal.
There is, therefore, a need in a high resolution DAC for a current source in which the correct current relationship is maintained between the currents of the binary-weighted current source array and the currents of the binary-weighted cascode current divider.